SM=SM_0, PHYM=PHYM_0, PHYW=PHYW_0
Hardware General
| PHYW | Data width of the transciever connected to the controller core. PHYW bit reset value is 0 (PHYW_0): 8 bit wide data bus Software non-programmable 1 (PHYW_1): 16 bit wide data bus Software non-programmable 2 (PHYW_2): Reset to 8 bit wide data bus Software programmable 3 (PHYW_3): Reset to 16 bit wide data bus Software programmable |
| PHYM | Transciever type 0 (PHYM_0): UTMI/UMTI+ 1 (PHYM_1): ULPI DDR 2 (PHYM_2): ULPI 3 (PHYM_3): Serial Only 4 (PHYM_4): Software programmable - reset to UTMI/UTMI+ 5 (PHYM_5): Software programmable - reset to ULPI DDR 6 (PHYM_6): Software programmable - reset to ULPI 7 (PHYM_7): Software programmable - reset to Serial |
| SM | Serial interface mode capability 0 (SM_0): No Serial Engine, always use parallel signalling. 1 (SM_1): Serial Engine present, always use serial signalling for FS/LS. 2 (SM_2): Software programmable - Reset to use parallel signalling for FS/LS 3 (SM_3): Software programmable - Reset to use serial signalling for FS/LS |